1. Field of the Invention
The present invention relates to a digital circuit for use in a circuit for producing a drive signal for an actuator or the like, and in particular to a digital circuit including a fail-safe circuit for forcibly and automatically holding an output of the digital circuit to a fail-safe side when a problem or anything unusual such as a stop or a frequency change of a system clock signal happens.
2. Description of the Background Art
In a conventional digital circuit, as shown in FIG. 1, processors PC.sub.1, PC.sub.2 . . . PC.sub.n are operated in synchronization with a system clock signal SC generated by an oscillator (OSC) 1 while input signals are fed to input terminals IN.sub.1, IN.sub.2 . . . IN.sub.n of the respective processors PC.sub.1, PC.sub.2 . . . PC.sub.n to output operation results to respective output terminals OUT.sub.1, OUT.sub.2 . . . OUT.sub.n to be connected to various actuators.
In FIG. 2, there is shown one embodiment of a processor PC which detects a running speed of an automobile and outputs an error signal when the running speed falls less than a certain value. In FIG. 3, there are shown waves forms of signals appearing in FIG. 2.
In FIGS. 2 and 3, a gate time generator 2 outputs a pulse signal b every certain times of the system clock signal (SC) a input from the OSC 1 to the gate time generator 2, and the pulse signal b as a reset signal for a counter 3 and a latch signal for a data latch 4 is fed to a reset terminal of the counter 3 and a latch-in terminal of the data latch 4.
A speed signal (SV) c for an automobile is input to an input terminal IN of the counter 3 which counts the number of the speed signals c while two reset signals b are fed from the gate time generator 2 to the counter 3 to output a count number signal d to the data latch 4. The data latch 4 latches the count number signal d and outputs a data signal e to a comparator 5 every time when the latch signal b is fed from the gate time generator 2 to the comparator 5.
In the comparator 5, the data signal e representing a running speed of the automobile is compared with a reference signal representing a predetermined reference running speed, and, when running speed of the automobile is lower than the predetermined reference running speed, the comparator 5 outputs an error signal f to an output terminal OUT.
When the error signal f output by the comparator 5 is sent to an actuator such as a speed controller (not shown) for the automobile in order to control a revolution speed of an engine so as not to fall less than the predetermined running speed of the automobile.
In this case, when a problem or anything unusual such as an accident or something wrong in the system clock signal a, for example, the system clock signal is stopped due to an inferior soldering in the OSC 1 or the frequency of the system clock signal is raised by an accident, the normal operation can not be carried out in the processor, and the output condition thereof becomes unstable. Hence, a problem may be caused in the output stage depending on an object to be controlled.
In FIG. 3, for instance, the system clock signal a is normally generated before the time t.sub.1, the frequency of the system clock signal a is raised between the times t.sub.1 and t.sub.2, and the system clock signal a is stopped after the time t.sub.2.
When the frequency of the system clock signal a is raised like in the time t.sub.1 to t.sub.2, the interval of the reset signals b to be fed to the counter 3 is shortened, and the counted value .gamma. represented by the count number signal d or the data signal e becomes less than the actual running speed of the automobile. Accordingly, the error signal f is output from the comparator 5, thereby erroneously increasing the running speed of the automobile.
Further, when the system clock signal a is stopped like after the time t.sub.2, the value of the data signal e output by the data latch 4 is not changed, and thus the value of the data signal e output just before the stop of the system clock signal is continuously output regardless of the actual running speed of the automobile. Hence, in case that the system clock signal a is stopped when the error signal f is output from the comparator 5, the comparator 5 keeps to output the error signal f. As a result, the actuator connected to the output terminal OUT continues to increase the running speed, which may cause the increase of the running speed with no limitation.
In FIG. 4, there is shown another conventional digital circuit which comprises an asynchronous octal counter 11 composed of first, second and third D-type flip flops 12, 13 and 14 connected in series, a NOR circuit 15 for operating a NOR of the two most significant bits of the counter 11, a D-type flip flop 16 for removing a hazard and an inverter 17. In the digital circuit, the system clock signal a is fed to an input terminal IN, and an actuator 18 represented by a load 19 and a MOS transistor 20 is coupled to an output terminal OUT. In FIG. 5, there are shown waveforms of signals shown in FIG. 4.
In the asynchronous counter 11, the system clock signal a is input to the first flip flop 12 and the output signals of the first and second flip flops 12 and 13 are fed to the respective second and third flip flops 13 and 14. In the counter 11, as well-known, T second delay is caused every one flip flop, and hence one bit output signal b, c and d of the first, second and third flip flops 12, 13 and 14 are delayed in order from the least significant bit by T second, 2T second and 3T second, respectively, with respect to the system clock signal a. Hence, when the NOR of the two significant bits of the output signals c and d in the counter 11 is operated, a hazard Z is caused in an output signal e of the NOR circuit 15. That is, the output signals c and d of the second and third flip flops 13 and 14 simultaneously become the "L" level for T second of the delay time between the falling of the output signal c and the rising of the output signal d, and the output signal e of the NOR circuit 15 becomes the "H" level for this T second of the delay time. The caused hazard Z can cause an erroneous operation and thus should be removed.
In this case, the hazard Z is removed by using the D-type flip flop 16 connected to the NOR circuit 15. That is, since the hazard Z is shifted by 2T second from the system clock signal a, the D-type flip flop 16 can not read the hazard Z and hence outputs a normal signal containing no hazard Z. The normal output signal of the D-type flip flop 16 is inverted in the inverter 17 to obtain an inverted signal f to be sent to the output terminal OUT. The inverted signal f is applied as a drive signal for the actuator 18 coupled to the output terminal OUT.
In FIG. 6, there is shown still another digital circuit. In this case, an asynchronous octal counter 21 is composed of first, second and third D-type flip flops 22, 23 and 24 connected in series. A one-shot circuit 25 is composed of two D-type flip flops 26 and 27 and an AND circuit 28 connected thereto. Three XOR circuits 29, 30 and 31 operate XORs between three output signals b, c and d of the first, second and third D-type flip flops 22, 23 and 24 and three input signals e, f and i to output three signals f, h and j, respectively, and these three output signals f, h and j are fed to a NOR circuit 32 for operating a NOR of these three signals f, h and j. An RS flip flop 33 receives an output signal k of the NOR circuit 32 and outputs a signal to an inverter 34 which inverts the signal and outputs an inverted signal m to an output terminal OUT.
Now, assuming that the input signals e, g and i have the "H", "L" and "H" levels, respectively, when the levels of the output signals b, c and d of the D-type flip flops 22, 23 and 24 of the counter 21 are coincident with the levels of the input signals e, g and i, respectively, the output signals f, h and j of the respective XOR circuits 29, 30 and 31 become the "L" level. When the output signals f, h and j of the XOR circuits 29, 30 and 31 become the "L" level at the same time, the NOR circuit 32 outputs the signal k having the "H" level to be input as a reset signal to the RS flip flop 33. The one-shot circuit 25 receives the most significant bit of the counter 21 and outputs a one-shot signal l as a set signal to the RS flip flop 33 to determine the frequency of the output signal m of the inverter 34.